In currently existing software defined radio (ES) product roadmaps, hardware is reconfigured, e.g. a field programmable gate array (FPGA) device, into circuits used to generate and receive waveforms. This may be accomplished before compiling. Often, there are more waveform circuits that may be used for a given mission than can fit in the given reconfigurable hardware. Further, during a campaign, new capabilities may be used and the ability to update a technique generator, where a technique defines a waveform with frequency, phase, and amplitude parameters as a function of time to add and remove capabilities may be performed. The hardware may be dynamically reconfigured to “swap” out waveform circuits during run-time.
Currently, waveform technique development takes weeks to months, wherein verification alone can take weeks. This is because techniques are currently monolithic and are not designed as independently operating modules where multiple techniques access the same resources. Moreover, there are occasionally more waveform circuits that may be used for a given mission than can fit in the given reconfigurable hardware.
Many methods exist that provide for partial reconfiguration approaches as well as dynamic, e.g., during runtime, reconfiguration approaches. Other dynamic reconfiguration approaches exhaustively compile a new version of a technique for each possible location the technique would be used on a FPGA. Still other dynamic reconfiguration approaches are verified such that the FPGA build is verified for the possible permutations.